Automated implementation of AI accelerators (FPGA-based or digital ASICs) for embedded systems (automotive, medical technology, industrial automation
Design flows and tools for targeting microcontroller and programmable system-on-chip (SoC) architectures as well as application-specific instruction set processors (e.g., RISC-V with custom function units)
Optimization of energy, performance, and resource requirements using compression techniques and hardware-aware neural architecture search (NAS)
Hardware/software co-design
AI processes for learning models in the design space exploration of hardware/software solutions
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